Paper Title
Verification Flow And Test Pattern Generation For Ip Centric Soc Validation And Testing Using Multiplexer Based Tam

Recent advances in IC design methodologies and manufacturing technologies have led to the integration of a complete system onto a single IC, called system on chip (SoC). Such a core based SoCs pose major challenges in the manufacturing test and design validation and debug domain. IP centric validation and testing in a system-on-chip (SoC) which is also referred as modular testing methodology, is recognized as an effective method to tackle the SoC testing problem; in which embedded cores are isolated from rest of the chip logic and direct accessibility is provided to them via chip primary IOs. The paper highlights the benefits and challenges of IP centric SoC validation-testing and gives an overview of multiplexer based TAM that we have implemented for targeted SSD controller SoC. The UVM environment based verification and test pattern generation framework that we are following is also briefly described in the paper.