Paper Title
Electrical Characterization of 3d Stacked Tsv with Voids

Through-silicon via (TSV) is a key component for the vertical interconnection of a 3D IC which can provide a significant performance improvement with greatly reduced physical length of channels among vertically integrated chips. TSV technology is used both in three-dimensional stacked ICs (3D-SICs), as well as in so-called 2.5D-SICs and supports high performance, small footprint and lower power consumption. With increasing demands for smaller, multi-functional electronic devices, 3D integration with TSV has attracted substantial attention and has been already on the way to commercialization. A TSV is a conducting copper nail, which provides an electrical connection though the substrate and is expected to be used extensively to provide high-speed interconnects between the top and bottom of the active dies. Duo to the TSV fabrication process, the void often exists in the TSV. As the void cannot easily being avoided, the electrical reliability of TSV integrated circuit (IC) shall be studied deeply for evaluating the electrical performance of the IC products and enhancing the TSVs reliability issues. This paper evaluates the electrical characteristics of TSV during the change of the void location and amounts using High Frequency Structure Simulator (HFSS) method. Keywords- 3D Stacked-ICs, Through Silicon Via (TSV), High Frequency Structure Simulator (HFSS).