Paper Title
JTAG Tap Controller Programming Using FPGA Board

Due to the increasing complexity of circuit boards, testing loaded boards is becoming prohibitively expensive and more difficult to perform. Board complexity has resulted from the rapid development of surface-mount technology and from the use of multi-layered boards. Finer pin spacing, high pin counts, and the use of double-sided mounted boards have also contributed to the increased cost and difficulty of traditional testing.In this paper Circuitry that may be built into Integrated circuits to assist in the test, maintenance and support of assembled printed circuit boards is defined. A test access port and boundary scan architecture for digital IC’s and for digital portions of mixed analog/digital IC’s is also defined. This test logic provides standardized approaches to test the inter-connections between IC’s once they have been assembled onto a printed circuit board or other substrate, testing the IC itself or pin reduction strategy. Keywords— Boundary scan, JTAG TAP controller, Instruction register, Bypass register, Identification register, Boundary- Scancell.