Paper Title
An Emission Reinforced Scheme For Pipeline Defense In Microprocessors

The hostile mounting of semiconductor technology has significantly increased the emission reinforced soft error rate in modern microprocessors. In the meantime, due to the increasing complexity of recent processor pipelines and the incomplete error-tolerance capabilities that former emission reinforced schemes can provide, the surviving pipeline protection schemes cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking design. The emission reinforced pipeline is achieved by incorporating SETT OFF-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection scheme is implemented in an Open RISC microprocessor in 65nm technology. A gate-level transient fault injection and analysis technique is used to evaluate the error-tolerance capability of the proposed reinforced pipeline design. The results show that compared to techniques such as TMR, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. In the meantime, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline defense technique to provide an upper level of consistency for different parts of the pipeline compared to former schemes. Key Terms- Fault-Tolerance, Consistency, Soft Errors, Error Tolerance, Timing Error, Fault Injection