Paper Title
An 8-Bit Pipeline ADC Scaled Down From 180nm To 90nmat 250mhz Nyquist Frequency To Obtain 6b ENOB And 40.4db SNDR

In this paper, an 8-bit Pipeline ADC, with 1V supply at 250MHz Nyquist frequency has been proposed. The ADC architecture uses 1.5bit stages as sub-ADCs for power reduction. This work targets 6b ENOB at both low and high input frequencies (ranging from 1-7MHz). SNDR is obtained 36.5dB and 40.4dB for 1MHz and 7MHz input frequencies respectively. The design has been implemented in 90nm CMOS technology. The comparative power consumption for 180nm and 90nm has also been shown. Index Terms-- Analog-to-Digital Converter (ADC), Interleaved Sample and Hold Circuit (ISHC), MultiplyingDAC (MDAC), high speed, low power.