Paper Title
Design Of Low Power Robust Symmetric Sram Cell Using Gated Ground Technique

Memory is an important part of any electronic device. In today's world static random access memory (SRAM) is widely used as memory. The major issues for design of SRAM are power loss, delay and stability. This paper presents a modified form of a symmetric eight-transistor SRAM bit-cell. In this paper transmission gate has been used as access transistor which provides rail-to-rail swing. Moreover, power consumption is reduced using gated ground technique. There is 32% power reduction in the proposed cell. All simulation are carried out in Spectre simulator of Cadence Virtuoso tool in 45nm technology process. All the circuits are operated at supply voltage of 1.3V. Index Terms—Symmetric SRAM, Data stability, Transmission gate, Gated-ground Technique.