Paper Title
Design Of Charge Pump and CSVCO Using Gm/Id Technique For Pll

Abstract
In this paper, it describes the design of PLL by using Phase-Frequency Detector, Drain switched Charge-Pump (CP), passive loop filter of second order, five-stage CSVCO (Current Starved VCO) circuit and Frequency Divider. In this work both Charge pump (CP) and CSVCO (Current Starved VCO) are implemented using Gm/Id Technique. The loop filter is used to obtain significant VCO gain with lock range from 456MHz-863MHz and have reduced lock time. The transistor sizing can influence the oscillation frequency range for the CSVCO which is 600 MHz-1.312 GHz, and the total power dissipated by the PLL is 22.895 mW with less area. By Utilizing 0.18um CMOS technology and a 1.8V supply voltage, the PLL is simulated and the lock time of 1.72 μs is obtained. Keywords - PLL, PFD, CSVCO, Gm/Id, Lock Time, CMOS, Charge Pump