Paper Title
Survey of Different Full Adder Circuits for Low Power Consumption

In this paper, we survey different techniques for low power consumption for 1-bit full adder circuits. The circuits are optimized for power efficiency at 180nm CMOS technology. The power consumption is mainly dependent on switching activity of transistor, node capacitance and circuit size. The circuit designed in subthreshold region consumes less power. Keywords - Full Adder Circuit, Low Power Consumption, Subthreshold Region.