Paper Title
Implementation of Fast Multiplier

Multiplication is one of four elementary arithmetic operations. As people are witnessing a huge growth in engineering and technology, the field of Very Large-Scale Integration (VLSI) has shown a rapid advancement too and has led to increasing demand for high speed processing. While implementing a crucial vlsi system, the high speed and low delay consuming units are very much important. Hence the multiplier is more in imposition in terms of processor design and delay reduction. Therefore, we intend to provide our research paper on distinct types of adders and various multipliers which are made with the help of these adders using an algorithm which directly approaches to the low time delay and high processing speed of the multiplier units. The Karatsuba algorithm. Karatsuba Algorithm was discovered by Dr. Anatoly Karatsuba. There are many uses of the above algorithm whether from finite field multiplication techniques or the reduction of complexity of operation. Many new multipliers which are based on the design of Karatsuba algorithm have been recently introduced. A proper example of this algorithm will be (KA) based systolic multiplier.Therefore, we intend to show our work in implementing a multiplier unit with the help of Karatsuba algorithm and show the difference in the delay of the circuit and the processing time. In addition, the codes are written in VHDL and implemented using ISE simulator.