Paper Title
Fault-Tolerant Network Interfaces For Networks-On-Chip Using Secded Technique

As the complexity of designs increases and technology scales down into the deep-submicron domain, the probability of malfunctions and failures in the Networks-on-Chip (NoCs) components increases. In this work, we focus on the study and evaluation of techniques for increasing reliability and resilience of Network Interfaces (NIs) within NoC-based Multiprocessor System-on-Chip (MPSoC) architectures. NIs act as interfaces between IP cores and the communication infrastructure; the faulty behavior of one of them could affect therefore the overall system. In this work, we propose a functional fault model for the NI components by evaluating their susceptibility to faults. We present a fault-tolerant solution that can be employed for mitigating the effects of both permanent and temporary faults in the NI.